Various electronic devices such as but not limited to Ahuja compensation circuits include high swing cascode biasing circuits. These circuits include components such as capacitors, resistors and/or transistors that produce dominant and/or non-dominant poles. The relative location of the poles in the frequency domain may adversely impact the frequency response of the high swing cascode biasing circuit.
Referring now to FIG. 1, a high swing cascode biasing circuit 10 includes a biasing circuit 12 and a current mirror circuit 14. The biasing circuit 12 generates a cascode bias 15 and a main bias 16, which are output to the current mirror circuit 14. The biasing circuit 12 includes first, second, third and fourth transistors 18, 20, 24 and 26, respectively. In this implementation, the first, second, third, and fourth transistors 18, 20, 24, and 26, respectively, are metal-oxide semiconductor field-effect transistors (MOSFETs) that have gates, sources, and drains, although other transistor types may be used.
In one approach, a source (or second terminal) of the first transistor 18 communicates with a drain (or first terminal) of the second transistor 20. A gate (or control terminal) of the second transistor 20 communicates with a gate and a drain of the first transistor 18.
A source of the third transistor 24 communicates with a drain of the fourth transistor 26. A gate of the fourth transistor 26 communicates with a drain of the third transistor 24. The gate of the first transistor 18 communicates with the gate of the third transistor 24. The drains of the first and third transistors 18 and 24, respectively, communicate with first and second current sources 28 and 30, respectively. The first and second current sources 28 and 30, respectively, communicate with a supply potential 32. Sources of the second and fourth transistors 20 and 26, respectively, communicate with a ground potential 34.
The current mirror circuit 14 includes fifth and sixth transistors 36 and 38, respectively. A source of the fifth transistor 36 communicates with a drain of the sixth transistor 38. The gate of the third transistor 24 communicates with a gate of the fifth transistor 36. The gate of the fourth transistor 26 communicates with a gate of the sixth transistor 38. A first end of a first capacitor 40 communicates with the source of the fifth transistor 36. A second end of the first capacitor 40 and a source of the sixth transistor 38 communicate with the ground potential 34. A load current 42 flows into the drain of the fifth transistor 36.
Since the load current 42 may be part of a signal path 43, it is important for the pole that is associated with the fifth transistor 36 and the first capacitor 40 to occur at a high frequency. The bandwidth of the high swing cascode biasing circuit 10 is equal to
      1          RC      L        ,where R is resistance of the fifth transistor 36 and CL is the capacitance of the first capacitor 40. Since the resistance of the fifth transistor 36 is equal to
      1          g              m        1              ,where gm1 is the transconductance of the fifth transistor 36, the bandwidth is equal to
      1                  (                  1                      g                          m              1                                      )            ⁢              C        L              =                    g                  m          1                            C        L              .  
To increase bandwidth of the signal path 43, either the transconductance gm1 of the fifth transistor 36 is increased or the capacitance CL of the first capacitor 40 is decreased. However, some applications such as Ahuja compensation circuits may require the capacitance CL to remain relatively fixed. In this case, the transconductance gm1 of the fifth transistor 36 is increased to increase the bandwidth.
There are typically two ways to increase the transconductance gm of a transistor. First, a channel width of the transistor may be increased to increase the transconductance gm since the transconductance increases as the channel width increases. However, current also increases as the channel width increases. Increasing current also increases power dissipation, which is undesirable. Additionally, increasing the channel width increases parasitic capacitance.
Referring now to FIG. 2A, another way to increase the transconductance of the fifth transistor 36 is to create a feedback loop and to amplify the feedback. A high swing cascode biasing circuit 52 that is shown in FIG. 2A includes a frequency boosting circuit 53 that is located between the current biasing circuit 12 and the current mirror 14. The frequency boosting circuit 53 includes a feedback loop 56. The gate of a third transistor 24 no longer communicates with the gate of the fifth transistor 36 as shown in FIG. 1. A gate of a seventh transistor 58 communicates with the source of the fifth transistor 36. A drain of the seventh transistor 58 communicates with the gate of the fifth transistor 36.
A first end of a second capacitor 60 communicates with the drain of the seventh transistor 58. The drain of the seventh transistor 58 communicates with a third current source 62. A second end of the second capacitor 60 and a source of the seventh transistor 58 communicate with the ground potential 34. The third current source 62 communicates with the supply potential 32. By adding an amplifier in the feedback loop 56, the output impedance, Rout, of the feedback branch 54 is reduced. The transconductance of the fifth transistor 36 increases as the output impedance decreases.
The following discussion sets forth the bandwidth of the circuit in FIG. 2A. In order to derive the bandwidth, an open loop response technique is used. The open loop response technique provides information relating to the bandwidth and maximum achievable bandwidth of a circuit. The DC gain of the open loop response is determined by opening the feedback loop and attaching a voltage source to one end of the opened feedback loop. The output voltage is sensed at the other end of the opened feedback loop.
To derive the bandwidth, the DC gain of the open loop response and the first dominant pole P1 are found. Assuming stable operation, there is only one pole P1 that is located below a crossover frequency. The crossover frequency is the product of the DC gain of the open loop response and the first dominant pole P1. The crossover frequency defines the bandwidth of the closed loop amplifier. The maximum available bandwidth is related to the second non-dominant pole P2.
Referring now to FIG. 2B, the response of the open loop circuit of FIG. 2A is shown. The circuit has a first pole
      g    m1        C    L  and a second pole
      1                  R        out            ⁢              C        p              .In FIG. 2B, we assume that the first pole
      g    m1        C    L  is dominant and that the second pole
  1            R      out        ⁢          C      p      is non-dominant. The DC gain of the open loop response is gm2Rout. Multiplying the DC gain of the open loop response with the dominant pole P1 results in the crossover frequency of
      g    m2    ⁢      R    out    ⁢                    g        m1                    C        L              .  The non-dominant pole at
  1            R      out        ⁢          C      p      relates to a barrier frequency or maximum achievable bandwidth. The crossover frequency
      g          m      2        ⁢            R      out        ⁡          (                        g                      m            1                                    C          L                    )      must be lower than the non-dominant pole,
      1                  R        out            ⁢              C        p              ,for the circuit to be stable. Therefore, a significant limitation exists on the overall bandwidth when
      g          m      1            C    L  is dominant.
In FIG. 2C, we will assume that the first pole
      g          m      1            C    L  is non-dominant and that the second pole is dominant
      1                  R        out            ⁢              C        p              .The DC gain of the open loop response is gm2Rout. Multiplying the DC gain of the open loop response with the dominant pole P1 results in the crossover frequency of
      g    m2    ⁢      R    out    ⁢            1                        R          out                ⁢                  C          p                      .  The non-dominant pole at
      g          m      1            C    L  relates to a barrier frequency or maximum achievable bandwidth.
It is desirable for the overall bandwidth,
            g              m        1                    C      L        ,to be high but
      g          m      2            C    p  must be lower than
      g          m      1            C    L  for the circuit to be stable. The operating frequency of the circuit is less than or equal to
            g              m        2                    C      p        ,which is less than
            g              m        1                    C      L        .Therefore, the frequency of the circuit never reaches
            g              m        1                    C      L        .Additionally, the high swing cascode biasing circuit 52 in FIG. 2A dissipates more power than the high swing cascode biasing circuit 10 of FIG. 1 due to the addition of the amplified feedback loop 56.